(1) Field of the Invention
The present invention relates to a MOS static RAM constructed with MOS transistors forming flip-flops as memory cells; a high-level supply voltage drop detection circuit, used in the MOS static RAM, for detecting a high-level supply voltage drop; a complementary signal transition detection circuit for detecting a transition of complementary signals such as complementary address signals generated within the RAM; and a semiconductor device having a wiring pattern designed to improve the time margin between signals.
(2) Description of the Related Art
In recent years, with decreasing (memory) cell size and increasing memory capacity of MOS static RAMs, there have been arising problems such as decreased soft error resistance of the cells and increased current consumption during standby, and these problems need urgent solution.
For MOS static RAMs, cell miniaturization is being pushed forward to increase the memory capacity; however, cell miniaturization involves a decrease in node parasitic capacitance, and hence a decrease in the amount of charge with which a node is charged when it is to be set to a high level. This decrease in the charge amount has been a major cause of decreased soft error resistance of the cells. The decrease of the soft error resistance due to cell miniaturization becomes greater as a high-level voltage to be applied to a node is reduced.
On the other hand, lower power dissipation is demanded of the MOS static RAM, and low-dissipation type MOS static RAMs have been made available for practical use. In such low-dissipation type MOS static RAMs, most of the standby power dissipation is due to the cell data retention current. If the supply voltage is reduced to reduce the cell data retention current for lower power consumption, the memory cell node voltage will drop, causing a further drop in the soft error resistance and hence the inability to obtain the necessary reliability of the device.
In particular, in a MOS static RAM having a memory cell structure of high resistance load type that permits reduced memory cell size and increased integration, a certain amount of cell data retention current is needed to ensure cell data retention, and there is a limit to increasing the load resistance value. Accordingly, increasing the memory cell density involves an increase in the cell data retention current as a whole, which has impeded efforts to further reduce the power consumption.
As described above, low-dissipation type MOS static RAMs have had the problem that sufficient soft error resistance cannot be obtained, since power consumption increases if sufficient soft error resistance is to be ensured.
Generally, the MOS static RAM has the problem that if the cell size is reduced, the dielectric strength of the insulating film decreases and the voltage of the same magnitude as is normally possible cannot be applied to the RAM internal circuitry. To avoid this problem, there are such semiconductor devices that contain a supply voltage reducing circuit to reduce the voltage to be applied to internal circuitry. On the other hand, it is often practiced to reduce the supply voltage to achieve lower power consumption. In some semiconductor devices, a voltage raising circuit is provided to prevent the voltage to be supplied to internal circuitry from dropping in the event that the external supply voltage drops.
For example, Japanese Unexamined Patent Publication (Kokai) No. 62-17778 discloses a semiconductor memory that has a word line voltage raising circuit and that switches the word line voltage raising circuit by detecting the supply voltage.
On the other hand, Japanese Unexamined Patent Publication (Kokai) No. 2-183495 discloses a semiconductor memory having a supply voltage reducing circuit wherein an external supply voltage is supplied to a word line drive circuit when the internal voltage that the supply voltage reducing circuit produces drops below a predetermined value.
Furthermore, Japanese Unexamined Patent Publication (Kokai) No. 4-132084 discloses a semiconductor device having a voltage generation circuit for generating a plurality of voltages and a delivery circuit for delivering the different supply voltages produced by the voltage generation circuit to various circuit portions according to the operating conditions of the circuit portions, thus reducing power consumption in nonoperating portions.
In any of the above three prior art examples, the voltage to be applied to the internal circuitry is switched between two or more values to reduce power consumption and/or alleviate adverse effects caused by variations in the external supply voltage. As previously noted, in the low-dissipation type MOS static RAM, most of the standby power dissipation is due to the cell data retention current, but in any of the above three prior art examples, no particular description is given about reducing the cell data retention current during standby, nor is there any mention of measures against soft errors.
In low-dissipation type integrated circuit devices, the supply voltage is kept lower during standby than during active mode, to reduce the power consumption. When effecting such supply voltage switching, it is usual to switch the voltage to be supplied to the cell array to a higher voltage so that the stored information can be retained. It is therefore necessary to detect the supply voltage when it is switched to a lower voltage. To effect such voltage switching, there has previously been used a circuit that detects the voltage dropping to a predetermined voltage. When switching the voltage to be supplied to the cell array from one value to another, the voltage to be supplied to the cell array must be switched to the higher voltage immediately when the supply voltage switching to the lower voltage is detected. Various circuits have been used to detect the switching of the supply voltage to the lower voltage, but no circuits have been available that perfectly satisfy the above requirement.
For example, in the above Japanese Unexamined Patent Publication (Kokai) No. 62-177787, there is disclosed a circuit that detects the supply voltage dropping to a predetermined value; similar circuits are also disclosed in Japanese Unexamined Patent Publication (Kokai) Nos. 62-150586, 62-188090, 63-103978, and 3-238365. These circuits, however, have the same problem as described above.
Accordingly, there is a demand to provide a circuit that is capable of promptly detecting the switching of the supply voltage to the lower voltage by using simple circuitry constructed with ordinary transistors.
With recent increases in the operating speeds and functional capabilities of semiconductor devices, it is commonly practiced to detect transitions of various signals and utilize their detection signals. In semiconductor memories such as static RAMs, transitions of address signals are detected to reset internal circuits or limit the operating intervals. Since the detection signals generated by detecting these transitions serve as the basic signals for various operations, reliable detection sensitivity and high speed response are demanded. Such address signal transition detection signals are generated from address complementary signals, the address signals of opposite polarity generated within the semiconductor memory. The circuit designed to detect the address signal transitions is called an address transition detection (ATD) circuit.
Japanese Unexamined Patent Publication (Kokai) Nos. 59-151523 and 3-263688 disclose address transition detection circuits utilizing NAND circuits: Japanese Unexamined Patent Publication (Kokai) No. 59-151523 discloses an address transition detection circuit with simple circuitry, and Japanese Unexamined Patent Publication (Kokai) No. 3-263688 discloses an address transition detection circuit that generates stable pulses.
In a memory device, a transition detection circuit that generates a pulse by detecting an address signal transition is required not only to respond to signal transitions at high speed, as described above, but also to generate a pulse in response to each signal transition for a prescribed period starting from the instant of transition. This is necessary for reset operations, etc., within the memory device. This requirement means that even when successive transitions occur within a short period of time because of introduction of noise, etc., in the address pulses, a prescribed pulse must be generated in response to each transition, and that even when a long train of successive pulses occurs depending on the transition pattern, for the last occurring transition a pulse must be generated that stops at the end of the prescribed period.
However, the address transition detection circuits disclosed in the above Japanese Unexamined Patent Publication (Kokai) Nos. 59-151523 and 3-263688 are not designed to generate a pulse in response to such a signal transition for a predetermined period starting from the instant of transition, and therefore, have the problem that when used in a semiconductor memory such as a static RAM, proper operations may not be performed as bit line resets, etc., may not be performed in the case of address pulses containing noise, etc., that causes successive transitions within a short period of time.
In recent years, with increasing storage capacity of static RAMs and other semiconductor devices, the chip area has been increasing, and accordingly, signal delay due to increased signal line length and failure of synchronization with other signals due to such delay have been posing problems. It is therefore demanded that the circuits be designed by considering signal delays caused by increased wiring length of signal lines. According to prior known signal line wiring for a semiconductor device, it is practiced to lay out the signal lines so that each signal line is run over the shortest possible distance to reduce the signal propagation delay attributable to the signal line length.
Thus, in the prior known signal line wiring layout, since each signal line is run over the shortest possible distance and its signal propagation direction (wiring direction) is determined without considering the wiring directions of adjacent signal lines, there occurs a timing difference between signals in terms of propagation times because of the arrangement and increased length of the signal lines. This causes situations where in some circuit blocks the timing difference between input signals is relatively small, while in other circuit blocks, the timing difference is relatively large, the resulting problem being that where the timing difference is large, the relevant circuit blocks are prone to malfunction.
Japanese Unexamined Patent Publication (Kokai) No. 3-137886 discloses a semiconductor memory equipped with means for controlling the amount of propagation delay so that the propagation delay is substantially equal for all control signals supplied to address signal processing circuits arranged in different locations on the chip. Furthermore, Japanese Unexamined Patent Publication (Kokai) No. 3-48455 discloses a wiring pattern designed to reduce the amount of signal propagation delay, while in Japanese Unexamined Patent Publication (Kokai) No. 4-132242, there is disclosed a semiconductor device in which variations in the propagation time between signals propagating along the chip are reduced. However, in any of these prior art examples, there is no mention made of the malfunctioning caused by the timing difference resulting from the signals propagating in different directions, and with these prior art arrangements, it is not possible to solve this problem.